1. Field of the Invention
The present invention relates to a method for generating a failure detection test pattern for detecting a failure in a logical circuit and a test pattern generating system, and more particularly to a failure detection test pattern generating method which can shorten time required for the pattern generation and reduce the test pattern number and a test pattern generating system.
2. Description of the Related Art
In a conventional generation of the above type of test pattern, "test pattern generating process" for generating a test pattern to detect a single target failure which is determined in a circuit diagram and "failure simulation" for determining a failure which is detected by a given test pattern are performed.
Such a conventional test pattern generating method has disadvantages that when a test pattern for obtaining a high failure detection rate is generated, the possibility of increasing the total number of test patterns generated (test pattern length becomes long) becomes high and it is hard to shorten the test time.
In order to remedy the above disadvantages, for example, Japanese Patent Laid-Open Publication (Kokai) No. Heisei 5-341011 proposes a test pattern generating method which performs the test pattern generation and the failure simulation in combination. This test pattern generating method determines a single failure as a target failure, and when a pattern for detecting the target failure is obtained in multiple numbers by the test pattern generation, selects several patterns from the obtained patterns, performs the failure simulation on respective patterns, and determines a pattern, which can detect most failures at the time, among the obtained results as the test pattern with respect to the target failure, thereby enabling to decrease the total number of test patterns (test pattern length).
Now, description will be made of the test pattern generating method described in the above-described Japanese Patent Laid-Open Publication No. Heisei 5-341011 with reference to the flowchart of FIG. 6 and the circuit diagram of FIG. 7 which shows an example of the logical circuit on which the test patterns are generated. The logical circuit of FIG. 7 comprises a first AND gate G701 having inputs i2, i3 as input, a second AND gate G703 having a reverse signal of the input i3 from an inverter G702 and an input i4 as input, an OR gate G704 having the first and second AND gates G701, G703 as input, and a third AND gate G705 having an input i1 and the output of the OR gate G704 as input.
First, a failure table 800 is prepared as shown in FIG. 8 in step 601. It is judged in step 602 whether or not all failures are detected, and if not, a single failure target is taken from undetected failures and determined as a target failure (step 603). First, a 0 degeneracy failure at an output f1 (stuck-at-0, hereinafter referred to as "f1/sa0") of the gate G705 is determined to be a target failure.
It is judged in step 604 whether or not the failure f1/sa0 has been detected, and if not, a test pattern for detecting the failure f1/sa0 is generated in step 605. In the logical circuit shown in FIG. 7, test patterns by which the failure f1/sa0 is detected are four of (i1, i2, i3, i4)=(1, 0, 0, 1), (1, 1, 0, 1), (1, 1, 1, 0) and (1, 1, 1, 1).
Since multiple test patterns are generated (step 606), the respective test patterns are subjected to the failure simulation (step 610), and respective failure detection numbers are recorded (step 611).
Then, a test pattern (1, 0, 0, 1) which has the most failure detection numbers is selected (step 612), and the failure table 800 is renewed (step 608).
A 1 degeneracy failure at the output f1 (stuck-at-1, hereinafter referred to as "f1/sa1") of the gate G705 is taken from the undetected failures and determined as a target failure (step 603). It is judged in step 604 whether or not the failure f1/sa1 has been detected, and if not, a test pattern for detecting the failure f1/sa1 is generated in step 605.
Test patterns by which the failure f1/sa1 is detected are 12 of (i1, i2, i3, i4)=(0, 0, 0, 0), (0, 0, 0, 1), (1, 0, 1, 0), (1, 0, 1, 1), (1, 1, 0, 0), (0, 0, 1, 0), (0, 0, 1, 1), (0, 1, 0, 0), (0, 1, 0, 1), (0, 1, 1, 0), (0, 1, 1, 1) and (1, 0, 0, 0). Since multiple test patterns are generated (step 606), the respective test patterns are subjected to the failure simulation (step 610), and the respective failure detection numbers are recorded (step 611).
Then, a test pattern (1, 0, 1, 1) which has the most failure detection numbers is selected (step 612), and the failure table 800 is renewed (step 608).
According to the flowchart shown in FIG. 6, the above-described respective steps are repeated until all failures are detected (step 602).
By the above process, the conventional test pattern generating method can detect a 0 degeneracy failure (sa0) and a 1 degeneracy failure (sa1) at inputs and outputs f1 to f11 of all gates by five test patterns (i1, i2, i3, i4)=(1, 0, 0, 1), (1, 0, 1, 1), (0, 0, 0, 1) and (1, 1, 0, 0) as shown in FIG. 8.
The above-described test pattern generating method needs to generate multiple test patterns with respect to a single target failure and, when the multiple test patterns are obtained, needs to perform the failure simulation on all the test patterns, so that it has a disadvantage that the time required to perform the failure simulation becomes enormous. Especially, large-scaling of semiconductor ICs and expansion of the failure simulation (namely, prolonging of the test pattern generating time) are serious issues.